Synthesis of Arithmetic Circuits: FPGAs, ASICs and Embedded Systems 


VHDL Models
Chapter 1: Introduction
Chapter 10: Circuit synthesis: general principlesExample 10.1 (combinational circuit) Example 10.2 (sequential circuit) Example 10.4 (long operand) Example 10.6 (selftimed)
Chapter 11: Adders and subtractorsExample 11.2 (ndigit baseB carrychain adder) Example 11.3 (ndigit baseB carryskip adder) Example 11.5 (ndigit baseB carryselect adder) Example 11.7 (twolevel ndigit baseB carrylookahead adder) Example 11.9 (s**2digit carrylookahead adder) Example 11.10 (ndigit BrentKung baseB prefix adder) Example 11.11 (moperand ndigit adder) Example 11.12 (moperand ndigit sequential carrysave adder) Example 11.14 (an adder substractor) Example 11.16 (B's complement addersubtractor) Example 11.17 (excessE adder and subtractor) Example 11.17bis (excessE adder and subtractor) Example 11.18 (signmagnitude adder)
Chapter 12: Adders and MultipliersExample 12.1 (ndigit by mdigit baseB basic multiplier) Example 12.2 (nbit by mbit base2 basic multiplier) Example 12.3 (ndigit by mdigit baseB basic sequential multiplier) Example 12.4 (nbit by mbit base2 ripplecarry multiplier) Example 12.5 (nbit by mbit base2 carrysave multiplier) Example 12.6 (nbit by mbit base2 ripple carry multiplier using 4 by 2 digits multiplier cell) Example 12.7 (nbit by mbit sequential multiplier for signed operands) Example 12.12 (nbit by mbit booth1 multiplier for signed operands) Example 12.13 (nbit by mbit booth2 multiplier for signed operands) Example 12.14 (nbit by mbit booth3 multiplier for signed operands)
Chapter 13: DividersExample 13.1 (nbits base2 restoring divider with pbits quotient and nbits remainder) Example 13.2 (nbits by mbits base2 restoring divider with natural quotient of nbits, and mbits remainder) Example 13.3 (BaseB ndigits divider with pdigits quotient and ndigits remainder) Example 13.4 (nbits base2 nonrestoring divider with pbits quotient and nbits remainder) Example 13.4bis (nbits by mbits base2 nonrestoring divider with quotient of nbits, and mbits remainder. There are 3 designs: X and Y naturals, X and Y integers, and integer X and natural Y in this last case the remainder R has one bit more (m+1 bits)). Example 13.6 (nonrestoring BaseB ndigits divider with pdigits quotient and ndigits remainder) Example 13.7 (nbits base2 SRT divider with pbits quotient and nbits remainder, 2’s complement remainder) Example 13.8 (nbits base2 SRT divider with pbits quotient and nbits remainder. The remainder in carry save format) Example 13.9 (nbits base4 SRT divider with pbits quotient and nbits remainder. The remainder is in 2’s complement) Example 13.10 (nbits base2 NewtonRaphson inverter with pbits quotient) Example 13.11 (nbits base2 goldschmidt divider with pbits quotient).
Extra examples of Chapter 13 div_nr_f_pipe.zip A pipelined version of a nbits base2 non restoring divider with pbits quotient and nbits remainder. Normalized positive number are required. The constant Depth controls the logic depht.div_nr_sec.zip A sequential version of a base2 non restoring divider. For naturals of X and Ybits. The constant GRAIN defines the amount of bits computed at each cycle. The algorithm needs XBITS/GRAIN + 1 cycles to calculate the result.
Chapter 15: Circuits for finite field operationsExample 15.1 (binary (B = 2) modulo m adders and subtractors) Example 15.2 (binary (B = 2) modulo m shiftandadd multiplier) Example 15.3 (binary Montgomery multiplier) Example 15.4 (computes x modulo 2^{n}  c, x being a 2.nbit number) Example 15.5 (a mod 239 reduction circuit) Example 15.6 (computes y.x modulo m, where x and y are two nbit numbers)
Chapter 16: Floatingpoint unitExample 16.7 (generic floatingpoint addersubtractor. It is made up of four blocks) Example 16.8 (generic floatingpoint multiplier. It is made up of four blocks) Example 16.9 (generic floatingpoint divider. It is made up of three blocks)

This site was last updated 11/02/07