library ieee; use ieee.std_logic_1164.all; package mypackage is constant n: natural := 8; constant m: natural := 4; constant logm: natural := 2; type long_operand is array(m-1 downto 0) of std_logic_vector(n-1 downto 0); end mypackage; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity example10_4 is port (x, y: in long_operand; clk, start, reset: in std_logic; done: out std_logic; z: out long_operand; carry: out std_logic ); end example10_4; architecture circuit of example10_4 is signal op_1, op_2, adder_out: std_logic_vector(n downto 0); signal c_in, c_out: std_logic; signal word_select: std_logic_vector(logm-1 downto 0); signal load: std_logic_vector(m-1 downto 0); signal load_cy: std_logic; subtype state is integer range -3 to m; signal current_state: state; begin --data path: op_1 <= ('0'&x(conv_integer(word_select))); op_2 <= ('0'&y(conv_integer(word_select))); adder_out <= op_1 + op_2 + c_in; c_out <= adder_out(n); process(clk) begin if reset = '1' then c_in <= '0'; elsif clk'event and clk = '1' then if load_cy = '1' then c_in <= c_out; end if; end if; end process; process(clk) begin if clk'event and clk = '1' then for i in 0 to m-1 loop if load(i) = '1' then z(i) <= adder_out(n-1 downto 0); end if; end loop; end if; end process; carry <= c_in; --control unit process(clk, reset) begin case current_state is when -3 => load <= conv_std_logic_vector(0, m); load_cy <= '0'; word_select <= conv_std_logic_vector(0, logm); done <= '1'; when -2 => load <= conv_std_logic_vector(0, m); load_cy <= '0'; word_select <= conv_std_logic_vector(0, logm); done <= '1'; when -1 => load <= conv_std_logic_vector(0, m); load_cy <= '0'; word_select <= conv_std_logic_vector(0, logm); done <= '1'; when 0 to m-1 => load <= conv_std_logic_vector(2**(current_state), m); load_cy <= '1'; word_select <= conv_std_logic_vector(current_state, logm); done <= '0'; when m => load <= conv_std_logic_vector(0, m); load_cy <= '0'; word_select <= conv_std_logic_vector(0, logm); done <= '1'; end case; if reset = '1' then current_state <= -3 ; elsif clk'event and clk = '1' then case current_state is when -3 => if start = '0' then current_state <= current_state + 1; end if; when -2 => if start = '1' then current_state <= current_state + 1; end if; when -1 => current_state <= current_state + 1; when 0 to m-1 => current_state <= current_state + 1; when m => current_state <= -3 ; end case; end if; end process; end circuit; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity test_example10_4 is end test_example10_4; architecture test of test_example10_4 is component example10_4 port (x, y: in long_operand; clk, start, reset: in std_logic; done: out std_logic; z: out long_operand; carry: out std_logic ); end component; signal x, y, z: long_operand; signal clk, start, reset: std_logic := '0'; signal done, carry: std_logic; begin device_under_test: example10_4 port map(x, y, clk, start, reset, done, z, carry); x(0) <= conv_std_logic_vector(123, n), conv_std_logic_vector(234, n) after 150 ns; x(1) <= conv_std_logic_vector(14, n), conv_std_logic_vector(15, n) after 150 ns; x(2) <= conv_std_logic_vector(245, n), conv_std_logic_vector(144, n) after 150 ns; x(3) <= conv_std_logic_vector(45, n), conv_std_logic_vector(36, n) after 150 ns; y(0) <= conv_std_logic_vector(31, n), conv_std_logic_vector(234, n) after 150 ns; y(1) <= conv_std_logic_vector(146, n), conv_std_logic_vector(15, n) after 150 ns; y(2) <= conv_std_logic_vector(245, n), conv_std_logic_vector(144, n) after 150 ns; y(3) <= conv_std_logic_vector(248, n), conv_std_logic_vector(36, n) after 150 ns; clk <= not(clk) after 5 ns; reset <= '1', '0' after 10 ns; start <= '0', '1' after 20 ns, '0' after 40 ns, '1' after 200 ns; end test;