package mypackage is constant n: natural := 10; end mypackage; library ieee; use ieee.std_logic_1164.all; --use ieee.std_logic_arith.all; --use ieee.std_logic_unsigned.all; use work.mypackage.all; entity example10_1 is port (x, y: in std_logic_vector(n-1 downto 0); c_in: in std_logic; z: out std_logic_vector(n-1 downto 0); c_out: out std_logic ); end example10_1; architecture circuit of example10_1 is signal p, g: std_logic_vector(n-1 downto 0); signal q: std_logic_vector(n downto 0); begin q(0) <= c_in; iterative_step: for i in 0 to n-1 generate p(i) <= x(i) xor y(i); g(i) <= y(i); with p(i) select q(i+1) <= q(i) when '1', g(i) when others; z(i) <= p(i) xor q(i); end generate; c_out <= q(n); end circuit; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity test_example10_1 is end test_example10_1; architecture test of test_example10_1 is component example10_1 port ( x, y: in std_logic_vector(n-1 downto 0); c_in: in std_logic; z: out std_logic_vector(n-1 downto 0); c_out: out std_logic ); end component; signal x, y, z: std_logic_vector(n-1 downto 0); signal c_in, c_out: std_logic; begin device_under_test: example10_1 port map(x, y, c_in, z, c_out); x <= conv_std_logic_vector(729, n), conv_std_logic_vector(14, n) after 10 ns, conv_std_logic_vector(322, n) after 20 ns, conv_std_logic_vector(45, n) after 30 ns; y <= conv_std_logic_vector(314, n), conv_std_logic_vector(415, n) after 10 ns, conv_std_logic_vector(322, n) after 20 ns, conv_std_logic_vector(1023, n) after 30 ns; c_in <= '0', '1' after 20 ns; end test;