library ieee; use ieee.std_logic_1164.all; package mypackage is constant n: natural := 8; constant m: natural := 4; constant logm: natural := 2; type operands is array(m-1 downto 0) of std_logic_vector(n-1 downto 0); end mypackage; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity example11_10 is port (x: in operands; clk, start, reset: in std_logic; done: out std_logic; z: inout std_logic_vector(n-1 downto 0) ); end example11_10; architecture circuit of example11_10 is signal adder_out, op_1: std_logic_vector(n-1 downto 0); signal operand_select: std_logic_vector(logm-1 downto 0); signal load, clear: std_logic; subtype state is integer range -3 to m; signal current_state: state; begin --data path: op_1 <= x(conv_integer(operand_select)); adder_out <= op_1 + z; process(clk) begin if clear = '1' then z <= conv_std_logic_vector(0,n); elsif clk'event and clk = '1' then if load = '1' then z <= adder_out; end if; end if; end process; --control unit process(clk, reset) begin case current_state is when -3 => load <= '0'; clear <= '0'; operand_select <= conv_std_logic_vector(0, logm); done <= '1'; when -2 => load <= '0'; clear <= '0'; operand_select <= conv_std_logic_vector(0, logm); done <= '1'; when -1 => load <= '0'; clear <= '1'; operand_select <= conv_std_logic_vector(0, logm); done <= '1'; when 0 to m-1 => load <= '1'; clear <= '0'; operand_select <= conv_std_logic_vector(current_state, logm); done <= '0'; when m => load <= '0'; clear <= '0'; operand_select <= conv_std_logic_vector(0, logm); done <= '1'; end case; if reset = '1' then current_state <= -3 ; elsif clk'event and clk = '1' then case current_state is when -3 => if start = '0' then current_state <= current_state + 1; end if; when -2 => if start = '1' then current_state <= current_state + 1; end if; when -1 => current_state <= current_state + 1; when 0 to m-1 => current_state <= current_state + 1; when m => current_state <= -3 ; end case; end if; end process; end circuit; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity test_example11_10 is end test_example11_10; architecture test of test_example11_10 is component example11_10 port (x: in operands; clk, start, reset: in std_logic; done: out std_logic; z: inout std_logic_vector(n-1 downto 0) ); end component; signal x: operands; signal z: std_logic_vector(n-1 downto 0); signal clk, start, reset: std_logic := '0'; signal done: std_logic; begin device_under_test: example11_10 port map(x, clk, start, reset, done, z); x(0) <= conv_std_logic_vector(123, n), conv_std_logic_vector(234, n) after 150 ns; x(1) <= conv_std_logic_vector(14, n), conv_std_logic_vector(15, n) after 150 ns; x(2) <= conv_std_logic_vector(245, n), conv_std_logic_vector(144, n) after 150 ns; x(3) <= conv_std_logic_vector(45, n), conv_std_logic_vector(36, n) after 150 ns; clk <= not(clk) after 5 ns; reset <= '1', '0' after 10 ns; start <= '0', '1' after 20 ns, '0' after 40 ns, '1' after 200 ns; end test;