library ieee; use ieee.std_logic_1164.all; package mypackage is constant n: natural := 8; type seven_operands is array(0 to 6) of std_logic_vector(n-1 downto 0); type operands is array(0 to 30) of std_logic_vector(n-1 downto 0); end mypackage; library ieee; use ieee.std_logic_1164.all; entity full_adder is port (x, y, c_in: in std_logic; c_out, z: out std_logic ); end full_adder; architecture rtl of full_adder is begin z <= x xor y xor c_in; c_out <= ((x and y) or (x and c_in) or (y and c_in)); end rtl; library ieee; use ieee.std_logic_1164.all; entity seven_to_three is port (x_0, x_1, x_2, x_3, x_4, x_5, x_6: in std_logic; y_2, y_1, y_0: out std_logic ); end seven_to_three; architecture circuit of seven_to_three is component full_adder port (x, y, c_in: in std_logic; c_out, z: out std_logic ); end component; signal a, b, c, d, e: std_logic; begin fa_1: full_adder port map(x_3, x_4, x_5, b, a); fa_2: full_adder port map(x_0, x_1, x_2, d, c); fa_3: full_adder port map(c, a, x_6, e, y_0); fa_4: full_adder port map(d, b, e, y_2, y_1); end circuit; library ieee; use ieee.std_logic_1164.all; use work.mypackage.all; entity stored_carry_encoder is port (x_0, x_1, x_2, x_3, x_4, x_5, x_6: in std_logic_vector(n-1 downto 0); u, v, w: out std_logic_vector(n-1 downto 0) ); end stored_carry_encoder; architecture circuit of stored_carry_encoder is component seven_to_three port (x_0, x_1, x_2, x_3, x_4, x_5, x_6: in std_logic; y_2, y_1, y_0: out std_logic ); end component; signal v_n, w_n, w_nn: std_logic; begin v(0) <= '0'; w(1) <= '0'; w(0) <= '0'; main_loop: for i in 0 to n-3 generate iterative_step: seven_to_three port map (x_0(i),x_1(i),x_2(i),x_3(i),x_4(i),x_5(i),x_6(i), w(i+2), v(i+1), u(i)); end generate; second_last_step: seven_to_three port map (x_0(n-2),x_1(n-2),x_2(n-2),x_3(n-2),x_4(n-2),x_5(n-2),x_6(n-2), w_n, v(n-1), u(n-2)); last_step: seven_to_three port map (x_0(n-1),x_1(n-1),x_2(n-1),x_3(n-1),x_4(n-1),x_5(n-1),x_6(n-1), w_nn, v_n, u(n-1)); end circuit; library ieee; use ieee.std_logic_1164.all; use work.mypackage.all; entity test_encoder is end test_encoder; architecture test of test_encoder is component stored_carry_encoder port (x_0, x_1, x_2, x_3, x_4, x_5, x_6: in std_logic_vector(n-1 downto 0); u, v, w: out std_logic_vector(n-1 downto 0) ); end component; signal x_0, x_1, x_2, x_3, x_4, x_5, x_6: std_logic_vector(n-1 downto 0); signal u, v, w: std_logic_vector(n-1 downto 0); signal x: seven_operands; begin x <= ("10010010", "00111110", "01011011", "11110011", "00101101", "11100110", "01101101"); x_0 <= x(0); x_1 <= x(1); x_2 <= x(2); x_3 <= x(3); x_4 <= x(4); x_5 <= x(5); x_6 <= x(6); device_under_test: stored_carry_encoder port map (x_0, x_1, x_2, x_3, x_4, x_5, x_6, u, v, w); end test; library ieee; use ieee.std_logic_1164.all; use work.mypackage.all; entity carry_save_tree is port (x_0, x_1, x_2, x_3, x_4, x_5, x_6, x_7, x_8, x_9, x_10, x_11, x_12, x_13, x_14, x_15, x_16, x_17, x_18, x_19, x_20, x_21, x_22, x_23, x_24, x_25, x_26, x_27, x_28, x_29, x_30: in std_logic_vector(n-1 downto 0); y, z, w: out std_logic_vector(n-1 downto 0) ); end carry_save_tree; architecture circuit of carry_save_tree is component stored_carry_encoder port (x_0, x_1, x_2, x_3, x_4, x_5, x_6: in std_logic_vector(n-1 downto 0); u, v, w: out std_logic_vector(n-1 downto 0) ); end component; signal a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12: std_logic_vector(n-1 downto 0); signal b1, b2, b3, b4, b5, b6: std_logic_vector(n-1 downto 0); begin encoder_1: stored_carry_encoder port map(x_2, x_3, x_4, x_5, x_6, x_7, x_8, a1, a2, a3); encoder_2: stored_carry_encoder port map(x_9, x_10, x_11, x_12, x_13, x_14, x_15, a4, a5, a6); encoder_3: stored_carry_encoder port map(x_16, x_17, x_18, x_19, x_20, x_21, x_22, a7, a8, a9); encoder_4: stored_carry_encoder port map(x_23, x_24, x_25, x_26, x_27, x_28, x_29, a10, a11, a12); encoder_5: stored_carry_encoder port map(x_1, a1, a2, a3, a4, a5, a6, b1, b2, b3); encoder_6: stored_carry_encoder port map(a7, a8, a9, a10, a11, a12, x_30,b4, b5, b6); encoder_7: stored_carry_encoder port map(x_0, b1, b2, b3, b4, b5, b6, y, z, w); end circuit; library ieee; use ieee.std_logic_1164.all; use work.mypackage.all; entity test_carry_save is end test_carry_save; architecture test of test_carry_save is component carry_save_tree port (x_0, x_1, x_2, x_3, x_4, x_5, x_6, x_7, x_8, x_9, x_10, x_11, x_12, x_13, x_14, x_15, x_16, x_17, x_18, x_19, x_20, x_21, x_22, x_23, x_24, x_25, x_26, x_27, x_28, x_29, x_30: in std_logic_vector(n-1 downto 0); y, z, w: out std_logic_vector(n-1 downto 0) ); end component; signal x_0, x_1, x_2, x_3, x_4, x_5, x_6, x_7, x_8, x_9, x_10, x_11, x_12, x_13, x_14, x_15, x_16, x_17, x_18, x_19, x_20, x_21, x_22, x_23, x_24, x_25, x_26, x_27, x_28, x_29, x_30: std_logic_vector(n-1 downto 0); signal y, z, w: std_logic_vector(n-1 downto 0); signal x: operands; begin device_under_test: carry_save_tree port map(x_0, x_1, x_2, x_3, x_4, x_5, x_6, x_7, x_8, x_9, x_10, x_11, x_12, x_13, x_14, x_15, x_16, x_17, x_18, x_19, x_20, x_21, x_22, x_23, x_24, x_25, x_26, x_27, x_28, x_29, x_30, y, z, w); x <= ("10010010", "00111110", "01011011", "11110011", "00101101", "11100110", "01101101", "10010010", "00111110", "01011011", "11110011", "00101101", "11100110", "01101101", "10010010", "00111110", "01011011", "11110011", "00101101", "11100110", "01101101", "10010010", "00111110", "01011011", "11110011", "00101101", "11100110", "01101101", "10010010", "00111110", "01011011"); x_0 <= x(0); x_1 <= x(1); x_2 <= x(2); x_3 <= x(3); x_4 <= x(4); x_5 <= x(5); x_6 <= x(6); x_7 <= x(7); x_8 <= x(8); x_9 <= x(9); x_10 <= x(10); x_11 <= x(11); x_12 <= x(12); x_13 <= x(13); x_14 <= x(14); x_15 <= x(15); x_16 <= x(16); x_17 <= x(17); x_18 <= x(18); x_19 <= x(19); x_20 <= x(20); x_21 <= x(21); x_22 <= x(22); x_23 <= x(23); x_24 <= x(24); x_25 <= x(25); x_26 <= x(26); x_27 <= x(27); x_28 <= x(28); x_29 <= x(29); x_30 <= x(30); end test;