library ieee; use ieee.std_logic_1164.all; package mypackage is constant B: natural := 10; subtype digit is natural range 0 to B-1; type digit_vector is array (natural range <>) of digit; constant n: natural := 4; constant excess: digit_vector(n downto 0) := (0, B/2, others => 0); constant minus_excess: digit_vector(n downto 0) := (B-1, B/2-1, others => B-1); end mypackage; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity example11_16bis is port (x, y: in digit_vector(n-1 downto 0); b_in: in std_logic; z: out digit_vector(n-1 downto 0); ovf: out std_logic ); end example11_16bis; architecture circuit of example11_16bis is signal w: digit_vector(n downto 0); signal carries_1, carries_2: std_logic_vector(n downto 0); signal z_n: digit; begin --first adder: carries_1(0) <= '0'; adder_1: for i in 0 to n-1 generate iterative_step: w(i) <= (x(i) + excess(i) + conv_integer(carries_1(i))) mod B; carries_1(i+1) <= '0' when x(i) + excess(i) + conv_integer(carries_1(i)) < B else '1'; end generate; last_step_1: w(n) <= (excess(n) + conv_integer(carries_1(n))) mod B; --second adder: carries_2(0) <= not(b_in); adder_2: for i in 0 to n-1 generate iterative_step: z(i) <= (w(i) + (B-1-y(i)) + conv_integer(carries_2(i))) mod B; carries_2(i+1) <= '0' when w(i) + (B-1-y(i)) + conv_integer(carries_2(i)) < B else '1'; end generate; last_step_2: z_n <= (w(n) + (B-1) + conv_integer(carries_2(n))) mod B; ovf <= '1' when z_n > 0 else '0'; end circuit; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity test_example11_16bis is end test_example11_16bis; architecture test of test_example11_16bis is component example11_16bis port (x, y: in digit_vector(n-1 downto 0); b_in: in std_logic; z: out digit_vector(n-1 downto 0); ovf: out std_logic ); end component; signal x, y, z: digit_vector(n-1 downto 0); signal b_in, ovf: std_logic; begin device_under_test: example11_16bis port map(x, y, b_in, z, ovf); x <= (7,3,4,5), (2,6,5,5) after 100 ns, (7,3,4,5) after 200 ns, (2,6,5,5) after 300 ns ; y <= (6,6,7,4), (9,7,2,6) after 200 ns, (0,2,7,4) after 400 ns; b_in <= '0'; end test;