library ieee; use ieee.std_logic_1164.all; package mypackage is constant n: natural := 10; constant m: natural := 4; constant logm: natural := 2; type operand_matrix is array(0 to m-1) of std_logic_vector(n-1 downto 0); end mypackage; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity example10_2 is port (operands: in operand_matrix; clk, start, reset: in std_logic; done: out std_logic; z: out std_logic_vector(n-1 downto 0) ); end example10_2; architecture circuit of example10_2 is signal op_1, op_2, adder_out, reg_in, reg_out: std_logic_vector(n-1 downto 0); signal op_select: std_logic_vector(logm-1 downto 0); signal clear, load: std_logic; subtype state is integer range -3 to m; signal current_state: state; begin --data path: op_1 <= operands(conv_integer(op_select)); op_2 <= reg_out; adder_out <= op_1 + op_2; with clear select reg_in <= adder_out when '0', conv_std_logic_vector(0, n) when others; process(clk) begin if clk'event and clk = '1' then if load = '1' then reg_out <= reg_in; end if; end if; end process; z <= reg_out; --control unit process(clk, reset) begin case current_state is when -3 => clear <= '1'; load <= '0'; op_select <= conv_std_logic_vector(0, logm); done <= '1'; when -2 => clear <= '1'; load <= '0'; op_select <= conv_std_logic_vector(0, logm); done <= '1'; when -1 => clear <= '1'; load <= '1'; op_select <= conv_std_logic_vector(0, logm); done <= '1'; when 0 to m-1 => clear <= '0'; load <= '1'; op_select <= conv_std_logic_vector(current_state, logm); done <= '0'; when m => clear <= '0'; load <= '0'; op_select <= conv_std_logic_vector(0, logm); done <= '1'; end case; if reset = '1' then current_state <= -3 ; elsif clk'event and clk = '1' then case current_state is when -3 => if start = '0' then current_state <= current_state + 1; end if; when -2 => if start = '1' then current_state <= current_state + 1; end if; when -1 => current_state <= current_state + 1; when 0 to m-1 => current_state <= current_state + 1; when m => current_state <= -3 ; end case; end if; end process; end circuit; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity test_example10_2 is end test_example10_2; architecture test of test_example10_2 is component example10_2 port (operands: in operand_matrix; clk, start, reset: in std_logic; done: out std_logic; z: out std_logic_vector(n-1 downto 0) ); end component; signal operands: operand_matrix; signal clk, start, reset: std_logic := '0'; signal done: std_logic; signal z: std_logic_vector(n-1 downto 0); begin device_under_test: example10_2 port map(operands, clk, start, reset, done, z); operands(0) <= conv_std_logic_vector(729, n), conv_std_logic_vector(234, n) after 150 ns; operands(1) <= conv_std_logic_vector(14, n), conv_std_logic_vector(729, n) after 150 ns; operands(2) <= conv_std_logic_vector(322, n), conv_std_logic_vector(144, n) after 150 ns; operands(3) <= conv_std_logic_vector(45, n), conv_std_logic_vector(36, n) after 150 ns; clk <= not(clk) after 5 ns; reset <= '1', '0' after 10 ns; start <= '0', '1' after 20 ns, '0' after 40 ns, '1' after 200 ns; end test;