library ieee; use ieee.std_logic_1164.all; package mypackage is constant B: natural := 10; subtype digit is natural range 0 to B-1; type digit_vector is array (natural range <>) of digit; constant n: natural := 4; end mypackage; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity example11_17 is port (x, y: in digit_vector(n-2 downto 0); sign_x, sign_y: in std_logic; z: out digit_vector(n-1 downto 0); sign_z: out std_logic ); end example11_17; architecture circuit of example11_17 is signal minus_y: digit_vector(n-2 downto 0); signal operand_2, a, operand_2bis: digit_vector(n-1 downto 0); signal minus_a: digit_vector(n-1 downto 0); signal carries_1, carries_2: std_logic_vector(n-1 downto 0); begin invert_y: for i in 0 to n-2 generate minus_y(i) <= B-1-y(i); end generate; carries_1(0) <= sign_x xor sign_y; with carries_1(0) select operand_2(n-2 downto 0) <= y when '0', minus_y when others; with carries_1(0) select operand_2(n-1) <= 0 when '0', B-1 when others; adder_1: for i in 0 to n-2 generate iterative_step: a(i) <= (x(i) + operand_2(i) + conv_integer(carries_1(i))) mod B; carries_1(i+1) <= '0' when x(i) + operand_2(i) + conv_integer(carries_1(i)) < B else '1'; end generate; a(n-1) <= (operand_2(n-1) + conv_integer(carries_1(n-1))) mod B; invert_a: for i in 0 to n-1 generate minus_a(i) <= B-1-a(i); end generate; carries_2(0) <= '0' when a(n-1) < B/2 else '1'; with carries_2(0) select operand_2bis <= a when '0', minus_a when others; with carries_2(0) select sign_z <= sign_x when '0', sign_y when others; adder_2: for i in 0 to n-2 generate iterative_step: z(i) <= (operand_2bis(i) + conv_integer(carries_2(i))) mod B; carries_2(i+1) <= '0' when operand_2bis(i) + conv_integer(carries_2(i)) < B else '1'; end generate; z(n-1) <= (operand_2bis(n-1) + conv_integer(carries_2(n-1))) mod B; end circuit; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity test_example11_17 is end test_example11_17; architecture test of test_example11_17 is component example11_17 port (x, y: in digit_vector(n-2 downto 0); sign_x, sign_y: in std_logic; z: out digit_vector(n-1 downto 0); sign_z: out std_logic ); end component; signal x, y: digit_vector(n-2 downto 0); signal sign_x, sign_y, sign_z: std_logic; signal z: digit_vector(n-1 downto 0); begin device_under_test: example11_17 port map(x, y, sign_x, sign_y, z, sign_z); x <= (3,4,5), (8,1,1) after 400 ns; y <= (6,7,4), (5,7,4) after 100 ns, (2,1,0) after 300 ns, (6,7,4) after 400 ns, (9,7,4) after 500 ns, (8,1,0) after 700 ns; sign_x <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns, '0' after 400 ns, '1' after 500 ns, '0' after 700 ns; sign_y <= '0', '1' after 400 ns; end test;