-------------------------------------------------------------------------------- -- Simple testbench for "classic_multiplier" module (for m=8) -- -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; use work.mastrovito_multiplier_parameters.all; ENTITY test_mastrovito_mult_vhd IS END test_mastrovito_mult_vhd; ARCHITECTURE behavior OF test_mastrovito_mult_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT mastrovito_multiplication PORT( a : IN std_logic_vector(m-1 downto 0); b : IN std_logic_vector(m-1 downto 0); c : OUT std_logic_vector(m-1 downto 0) ); END COMPONENT; --Inputs SIGNAL a : std_logic_vector(m-1 downto 0) := (others=>'0'); SIGNAL b : std_logic_vector(m-1 downto 0) := (others=>'0'); --Outputs SIGNAL c : std_logic_vector(m-1 downto 0); BEGIN -- Instantiate the Unit Under Test (UUT) uut: mastrovito_multiplication PORT MAP( a => a, b => b, c => c ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; a <= "10101010"; b <= "10101010"; wait for 100 ns; a <= "10101010"; b <= "00000000"; wait for 100 ns; a <= "11111111"; b <= "10101010"; wait for 100 ns; a <= "10101010"; b <= "01010101"; wait for 100 ns; a <= "01010101"; b <= "01010101"; wait for 100 ns; wait; -- will wait forever END PROCESS; END;