---------------------------------------------------------------------------- -- Karatsuba Multiplier (Karatsuba_multiplier.vhd) -- -- Computes the polynomial multiplication using the -- Karatsuba decomposition. Only for even M -- ---------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity karatsuba_multiplier_even is generic (M: integer:= 8); port ( a, b: in std_logic_vector(M-1 downto 0); d: out std_logic_vector(2*M-2 downto 0) ); end karatsuba_multiplier_even; architecture simple of karatsuba_multiplier_even is component polynom_multiplier is generic (M: integer:= 8); port ( a, b: in std_logic_vector(M-1 downto 0); d: out std_logic_vector(2*M-2 downto 0) ); end component polynom_multiplier; constant half_M :integer := M/2; signal x0y0, x01y01: std_logic_vector(2*half_M-2 downto 0); signal x1y1: std_logic_vector(2*half_M-2 downto 0); signal x0_p_X1, y0_p_y1: std_logic_vector(half_M-1 downto 0); begin mult1: polynom_multiplier generic map(M => half_M) port map(a => a(half_M-1 downto 0), b => b(half_M-1 downto 0), d=> x0y0); mult2: polynom_multiplier generic map(M => half_M) port map(a => a(M-1 downto half_M), b => b(M-1 downto half_M), d=> x1y1); mult3: polynom_multiplier generic map(M => half_M) port map(a => x0_p_X1, b => y0_p_y1, d=> x01y01); gen_x0x1y0y1: for i in 0 to half_M-1 generate x0_p_X1(i) <= a(i) xor a(i + half_M); y0_p_y1(i) <= b(i) xor b(i + half_M); end generate; gen_prod1: for i in 0 to half_M-2 generate d(half_M + i) <= x01y01(i) xor x0y0(i) xor x1y1(i) xor x0y0(i+half_M); end generate; d(2*half_M-1) <= x01y01(half_M-1) xor x0y0(half_M-1) xor x1y1(half_M-1); gen_prod2: for i in half_M to 2*half_M-2 generate d(half_M + i) <= x01y01(i) xor x0y0(i) xor x1y1(i) xor x1y1(i-half_M) ; end generate; d(3*half_M-1) <= x1y1(half_M-1); d(half_M-1 downto 0) <= x0y0(half_M-1 downto 0); d(2*M-2 downto 3*half_M) <= x1y1(2*half_M-2 downto half_M); end simple;