-------------------------------------------------------------------------------- -- Test for Polynomial divider (ch6) (binary_algorithm_polynomials.vhd) -- -- Generates random vectors and multiply again -- using the LSE-first multiplier -- -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE IEEE.std_logic_arith.all; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; USE ieee.std_logic_textio.ALL; use ieee.math_real.all; -- for UNIFORM, TRUNC use work.binary_algorithm_polynomials_parameters.all; USE std.textio.ALL; ENTITY test_binary_div IS END test_binary_div; ARCHITECTURE behavior OF test_binary_div IS -- Component Declaration for the Unit Under Test (UUT1) component LSE_first_mod_f_mult_test2 is port( a, b: in polynomial; clk, reset, start: in std_logic; z: out polynomial; done: out std_logic ); end component; component binary_algorithm_polynomials is port( g, h: in polynomial; clk, reset, start: in std_logic; z: out polynomial; done: out std_logic ); end component; -- Internal signals SIGNAL clk, reset, start_div, start_mul, done_div, done_mul: std_logic; constant DELAY : time := 100 ns; constant PERIOD : time := 200 ns; constant DUTY_CYCLE : real := 0.5; constant OFFSET : time := 0 ns; constant NUMBER_TESTS: natural := 10; signal x, y, x_div_y, x_div_y_mul_y: polynomial; -- := (others => zero_coef); BEGIN -- Instantiate the Unit Under Test (UUT) uut1: binary_algorithm_polynomials port map ( g => x, h => y, clk => clk, reset => reset, start => start_div, z => x_div_y, done => done_div); uut2: LSE_first_mod_f_mult_test2 port map ( a => x_div_y, b => y, clk => clk, reset => reset, start => start_mul, z => x_div_y_mul_y, done => done_mul); PROCESS -- clock process for clk BEGIN WAIT for OFFSET; CLOCK_LOOP : LOOP clk <= '0'; WAIT FOR (PERIOD *(1.0 - DUTY_CYCLE)); clk <= '1'; WAIT FOR (PERIOD * DUTY_CYCLE); END LOOP CLOCK_LOOP; END PROCESS; tb_proc : PROCESS --generate values PROCEDURE gen_polynom(X : out polynomial; w: natural; s1, s2: inout Natural) IS VARIABLE i_x, i_p: natural; VARIABLE rand: real; BEGIN i_p := conv_integer(P); for i in 0 to M-1 loop UNIFORM(s1, s2, rand); i_x := INTEGER(TRUNC(rand * real(i_p))); x(i) := CONV_STD_LOGIC_VECTOR (i_x, K); end loop; END PROCEDURE; VARIABLE seed1, seed2: positive; VARIABLE i_x, i_y, i_p, i_z, i_yz_modp: integer; VARIABLE cycles, max_cycles, min_cycles, total_cycles: integer := 0; VARIABLE avg_cycles: real; VARIABLE initial_time, final_time: time; VARIABLE xx: polynomial ; BEGIN min_cycles:= 2**20; start_mul <= '0'; start_div <= '0'; reset <= '1'; WAIT FOR PERIOD; reset <= '0'; WAIT FOR PERIOD; for I in 1 to NUMBER_TESTS loop gen_polynom(xx, M, seed1, seed2); x <= xx; gen_polynom(xx, M, seed1, seed2); y <= xx; start_div <= '1'; initial_time := now; WAIT FOR PERIOD; start_div <= '0'; wait until done_div = '1'; final_time := now; cycles := (final_time - initial_time)/PERIOD; total_cycles := total_cycles+cycles; --ASSERT (FALSE) REPORT "Number of Cycles: " & integer'image(cycles) & " TotalCycles: " & integer'image(total_cycles) SEVERITY WARNING; if cycles > max_cycles then max_cycles:= cycles; end if; if cycles < min_cycles then min_cycles:= cycles; end if; WAIT FOR PERIOD; start_mul <= '1'; WAIT FOR PERIOD; start_mul <= '0'; wait until done_mul = '1'; WAIT FOR 2*PERIOD; IF ( x /= x_div_y_mul_y ) THEN ASSERT (FALSE) REPORT "ERROR!!! X /= X/Y * Y" SEVERITY ERROR; END IF; end loop; WAIT FOR DELAY; avg_cycles := real(total_cycles)/real(NUMBER_TESTS); ASSERT (FALSE) REPORT "Simulation successful!. MinCycles: " & integer'image(min_cycles) & " MaxCycles: " & integer'image(max_cycles) & " TotalCycles: " & integer'image(total_cycles) & " AvgCycles: " & real'image(avg_cycles) SEVERITY FAILURE; END PROCESS; END;