-------------------------------------------------------------------------------- -- -- VHDL Test Bench for module: Barret_reducer.vhd -- -- -- This testbench only works for N <= 24 and M = 239. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE IEEE.std_logic_arith.all; USE ieee.std_logic_signed.all; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; USE ieee.std_logic_textio.ALL; USE std.textio.ALL; use work.Barrett_reducer_package.all; ENTITY test_barrett_reduction_comb IS END test_barrett_reduction_comb; ARCHITECTURE behavior OF test_barrett_reduction_comb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT barrett_reducer_comb PORT( x : IN std_logic_vector(N-1 downto 0); z : OUT std_logic_vector(K-1 downto 0) ); END COMPONENT; --Inputs & Outputs SIGNAL x : std_logic_vector(N-1 downto 0) := (others=>'0'); SIGNAL z : std_logic_vector(K-1 downto 0); constant PERIOD : time := 200 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: barrett_reducer_comb PORT MAP( x => x, z => z ); tb_test : PROCESS --test the correctness of data VARIABLE TX_LOC : LINE; VARIABLE TX_STR : String(1 to 4096); Variable J: integer:= 239; BEGIN ASSERT (N < 25) REPORT "N is too big for an exhaustive Test Bench." SEVERITY FAILURE; WAIT FOR PERIOD; for I in 0 to 2**N -1 loop -- WAIT until (done = '1'); WAIT FOR PERIOD/2; x <= CONV_STD_LOGIC_VECTOR (I, N); WAIT FOR PERIOD; IF ( (I mod J) /= ieee.std_logic_unsigned.CONV_INTEGER(z) ) THEN write(TX_LOC,string'("ERROR!!! X=")); write(TX_LOC, x); write(TX_LOC,string'(" mod M=")); write(TX_LOC, m); write(TX_LOC,string'(" is Z=")); write(TX_LOC, z); write(TX_LOC,string'(" instead of:")); write(TX_LOC, I mod J); write(TX_LOC, string'(" ")); write(TX_LOC,string'(" (i=")); write(TX_LOC, i); write(TX_LOC,string'(" j=")); write(TX_LOC, j); write(TX_LOC, string'(")")); TX_STR(TX_LOC.all'range) := TX_LOC.all; Deallocate(TX_LOC); ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR; END IF; end loop; ASSERT (FALSE) REPORT "Simulation successful (not a failure). No problems detected. " SEVERITY FAILURE; END PROCESS; END;