---------------------------------------------------------------------------- -- Barret Reducer (barret_reducer.vhd) -- -- Computes the remainder (x mod m) using the -- Barret algorithm (combinatorial implementation) -- As C and M are constants, -- more efficient multipliers can be implemented. ---------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; package Barrett_reducer_package is constant N: natural := 24; constant K: natural := 8; constant M: std_logic_vector(K-1 downto 0) := "11101111"; --239d -- constant N: natural := 384; -- constant K: natural := 192; -- constant M: std_logic_vector(K-1 downto 0):= (64 => '0', others => '1'); --p192 -- constant C: std_logic_vector(N-K downto 0) := '1'&(X"12"); --for N=16 constant C: std_logic_vector(N-K downto 0) := '1'&(X"1235"); --for N=24 -- constant C: std_logic_vector(N-K downto 0) := '1'&(X"12358E"); --for N=32 -- constant C: std_logic_vector(N-K downto 0) := '1'&(X"12358E75D30336"); --for N=64 ((B**N)/M) -- constant C: std_logic_vector(N-K downto 0) := (192 => '1', 64 => '1', 0 => '1', others => '0'); --for p192 = 2**192 + 2**64 + 1 end Barrett_reducer_package; library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use work.Barrett_reducer_package.all; entity Barrett_reducer_comb is port ( x: in std_logic_vector (N-1 downto 0); z: out std_logic_vector (K-1 downto 0) ); end Barrett_reducer_comb; architecture rtl of Barrett_reducer_comb is signal mult_1: std_logic_vector(2*(N-K) + 2 downto 0); signal mult_2: std_logic_vector(2*K + 1 downto 0); signal q: std_logic_vector(K+1 downto 0); signal r, product: std_logic_vector(K+1 downto 0); signal r_minus_m, r_minus_2m: std_logic_vector(K+2 downto 0); --For Xilinx XST synthesis attribute mult_style: string; attribute mult_style of mult_1: signal is "kcm"; --"{auto|block|pipe_block|kcm|csd|lut|pipe_lut}"; attribute mult_style of mult_2: signal is "csd"; begin mult_1 <= x(N-1 downto K-1) * ('0' & C); q <= mult_1(N+2 downto N-K+1); mult_2 <= q * M; product <= mult_2(K+1 downto 0); r <= x(k+1 downto 0) - product; r_minus_m <= ('0' & r) - M; r_minus_2m <= ('0' & r) - (M & '0'); muxout: process(r, r_minus_m, r_minus_2m) begin if r_minus_m(K+2) = '1' then Z <= r(K-1 downto 0); elsif r_minus_2m(K+2) = '1' then Z <= r_minus_m(K-1 downto 0); else Z <= r_minus_2m(K-1 downto 0); end if; end process; end rtl;