library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; package my_package is constant m: integer := 163; constant logm: integer := 8; --constant logk: integer := 3; --constant exp_k: std_logic_vector(k-1 downto 0) := conv_std_logic_vector(17, k); --constant exp_k: std_logic_vector(k-1 downto 0) := x"11"; --constant exp_2k: std_logic_vector(k-1 downto 0) := conv_std_logic_vector(50, k); --constant exp_2k: std_logic_vector(k-1 downto 0) := x"32"; --constant p: std_logic_vector(k-1 downto 0) := conv_std_logic_vector(239, k); --constant p: std_logic_vector(k-1 downto 0) := x"EF"; --constant p_minus2: std_logic_vector(k-1 downto 0) := conv_std_logic_vector(237, k); --constant p_minus2: std_logic_vector(k-1 downto 0) := x"ED"; constant f1: std_logic_vector(162 downto 8) := (others => '0'); constant f0: std_logic_vector(7 downto 0) := "11001001"; constant f: std_logic_vector(162 downto 0) := f1&f0; end my_package; library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use work.my_package.all; entity polynomial_product is port ( a, b: in std_logic_vector(m-1 downto 0); clk, reset, start: in std_logic; z: inout std_logic_vector(m-1 downto 0); done: out std_logic ); end polynomial_product; architecture rtl of polynomial_product is signal c, next_z, reg_b: std_logic_vector(m-1 downto 0); signal b_i, load_b, shift_b, ce_z, clear_z: std_logic; subtype states is natural range 0 to m+2; signal current_state: states; begin by_x: for j in 1 to m-1 generate c(j) <= z(j-1) xor (f(j) and z(m-1)); end generate; c(0) <= f(0) and z(m-1); conditional_sum: for j in 0 to m-1 generate next_z(j) <= c(j) xor (a(j) and b_i); end generate; shift_register: process(clk) begin if clk'event and clk = '1' then if load_b = '1' then reg_b <= b; elsif shift_b = '1' then for i in m-1 downto 1 loop reg_b(i) <= reg_b(i-1); end loop; reg_b(0) <= '0'; end if; end if; end process shift_register; b_i <= reg_b(m-1); register_z: process(clk) begin if clk'event and clk = '1' then if clear_z = '1' then z <= (others => '0'); elsif ce_z = '1' then z <= next_z; end if; end if; end process register_z; control_unit: process(clk, reset, current_state) begin case current_state is when 0 to 1 => load_b <= '0'; shift_b <= '0'; ce_z <= '0'; clear_z <= '0'; done <= '1'; when 2 => load_b <= '1'; shift_b <= '0'; ce_z <= '0'; clear_z <= '1'; done <= '0'; when 3 to m+2 => load_b <= '0'; shift_b <= '1'; ce_z <= '1'; clear_z <= '0'; done <= '0'; end case; if reset = '1' then current_state <= 0; elsif clk'event and clk = '1' then case current_state is when 0 => if start = '0' then current_state <= current_state + 1; end if; when 1 => if start = '1' then current_state <= current_state + 1; end if; when 2 to m+1 => current_state <= current_state + 1; when m+2 => current_state <= 0; end case; end if; end process control_unit; end rtl; library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use work.my_package.all; entity algorithm12 is port ( g, h: in std_logic_vector(m-1 downto 0); clk, reset, start: in std_logic; z: out std_logic_vector(m-1 downto 0); done: out std_logic ); end algorithm12; architecture circuit of algorithm12 is component polynomial_product is port ( a, b: in std_logic_vector(m-1 downto 0); clk, reset, start: in std_logic; z: inout std_logic_vector(m-1 downto 0); done: out std_logic ); end component; signal sel: std_logic_vector(1 downto 0); signal start_product, product_done, ce_e, preset, inc: std_logic; signal second_operand, next_e, e: std_logic_vector(m-1 downto 0); subtype states is natural range 0 to 15; signal current_state: states; signal count: std_logic_vector(logm-1 downto 0); begin with sel select second_operand <= e when "00", h when "01", g when others; main_component: polynomial_product port map (e, second_operand, clk, reset, start_product, next_e, product_done); register_e: process(clk) begin if clk'event and clk = '1' then if preset = '1' then e(0) <= '1'; for i in 1 to m-1 loop e(i) <= '0'; end loop; elsif ce_e = '1' then e <= next_e; end if; end if; end process register_e; z <= e; counter: process(clk) begin if clk'event and clk = '1' then if preset = '1' then count <= (others => '0'); elsif inc = '1' then count <= count+1; end if; end if; end process counter; control_unit: process(clk, reset, current_state) begin case current_state is when 0 to 1 => sel <= "00"; start_product <= '0'; preset <= '0'; inc <= '0'; ce_e <= '0'; done <= '1'; when 2 => sel <= "00"; start_product <= '0'; preset <= '1'; inc <= '0'; ce_e <= '0'; done <= '0'; when 3 => sel <= "00"; start_product <= '0'; preset <= '0'; inc <= '0'; ce_e <= '0'; done <= '0'; when 4 => sel <= "00"; start_product <= '1'; preset <= '0'; inc <= '1'; ce_e <= '0'; done <= '0'; when 5 => sel <= "00"; start_product <= '0'; preset <= '0'; inc <= '0'; ce_e <= '0'; done <= '0'; when 6 => sel <= "00"; start_product <= '0'; preset <= '0'; inc <= '0'; ce_e <= '1'; done <= '0'; when 7 => sel <= "01"; start_product <= '1'; preset <= '0'; inc <= '0'; ce_e <= '0'; done <= '0'; when 8 => sel <= "01"; start_product <= '0'; preset <= '0'; inc <= '0'; ce_e <= '0'; done <= '0'; when 9 => sel <= "01"; start_product <= '0'; preset <= '0'; inc <= '0'; ce_e <= '1'; done <= '0'; when 10 => sel <= "00"; start_product <= '1'; preset <= '0'; inc <= '0'; ce_e <= '0'; done <= '0'; when 11 => sel <= "00"; start_product <= '0'; preset <= '0'; inc <= '0'; ce_e <= '0'; done <= '0'; when 12 => sel <= "00"; start_product <= '0'; preset <= '0'; inc <= '0'; ce_e <= '1'; done <= '0'; when 13 => sel <= "10"; start_product <= '1'; preset <= '0'; inc <= '0'; ce_e <= '0'; done <= '0'; when 14 => sel <= "10"; start_product <= '0'; preset <= '0'; inc <= '0'; ce_e <= '0'; done <= '0'; when 15 => sel <= "10"; start_product <= '0'; preset <= '0'; inc <= '0'; ce_e <= '1'; done <= '0'; end case; if reset = '1' then current_state <= 0; elsif clk'event and clk = '1' then case current_state is when 0 => if start = '0' then current_state <= current_state + 1; end if; when 1 => if start = '1' then current_state <= current_state + 1; end if; when 2 => current_state <= current_state + 1; when 3 => if count <= m-2 then current_state <= current_state + 1; else current_state <= 10; end if; when 4 => current_state <= current_state + 1; when 5 => if product_done = '1' then current_state <= current_state + 1; end if; when 6 => current_state <= current_state + 1; when 7 => current_state <= current_state + 1; when 8 => if product_done = '1' then current_state <= current_state + 1; end if; when 9 => current_state <= 3; when 10 => current_state <= current_state + 1; when 11 => if product_done = '1' then current_state <= current_state + 1; end if; when 12 => current_state <= current_state + 1; when 13 => current_state <= current_state + 1; when 14 => if product_done = '1' then current_state <= current_state + 1; end if; when 15 => current_state <= 0; end case; end if; end process control_unit; end circuit;